Thursday, June 13, 2002, 4:30 PM - 6:00 PM | Room: 292 SESSION 53    Circuit Effects in Static Timing    Chair: Jamil Kawa - Synopsys, Inc., Mountain View, CA Chair:    Organizers: Chandu Visweswariah, Louis Scheffer    Static timing analysis increasingly needs to take circuit effects into account. This session presents novel approaches to incorporating delay changes due to power/ground noise, interconnect loading and crosstalk during static timing. The final paper is devoted to a study of electrostatic discharge failures.      53.1 Coping with Buffer Delay Change Due to Power and Ground Noise    Speaker(s): Lauren Hui Chen - Avant! Corp., Fremont, CA    Author(s): Lauren Chen - Avant! Corp., Fremont, CA Malgorzata Marek-Sadowska - Univ. of California, Santa Barbara, CA Forrest Brewer - Univ. of California, Santa Barbara, CA      53.2 Osculating Thevenin Model For Predicting Delay and Slew of Capacitively Characterized Cells    Speaker(s): Bernard N. Sheehan - Mentor Graphics Corp., Wilsonville, OR    Author(s): Bernard N. Sheehan - Mentor Graphics Corp., Wilsonville, OR      53.3 Timed Pattern Generation for Noise-on-Delay Calculation    Speaker(s): Seung Hoon Choi - Purdue Univ., West Lafayette, IN    Author(s): Seung Hoon Choi - Purdue Univ., West Lafayette, IN Florentin Dartu - Intel Corp., Hillsboro, OR Kaushik Roy - Purdue Univ., West Lafayette, IN      53.4 VeriCDF: A New Verification Methodology for Charged Device Failures    Speaker(s): Jaesik Lee - Lucent Tech., Murray Hill, NJ    Author(s): Jaesik Lee - Lucent Tech., Murray Hill, NJ Ki Wook Kim - Pluris Inc., Cupertino, CA Sung Mo Steve Kang - Univ. of California, Santa Cruz, CA